Computer Organization And Architecture – William Stallings – 8th Edition


For undergraduates and professionals in computer science, computer engineering, and electrical engineering courses. Four-time winner of Text and Academic Author’s award for best Computer Science and Engineering text!
Learn the fundamentals of processor and computer design from the newest edition of this award winning text.

Four-time winner of the best Computer Science and Engineering textbook of the year award from the Textbook and Academic Authors Association, Computer Organization and Architecture: Designing for Performance provides a thorough discussion of the fundamentals of computer organization and architecture, covering not just processor design, but memory, I/O, and parallel systems.Coverage is supported by a wealth of concrete examples emphasizing modern RISC, CISC, and superscalar systems.

The eighth revision has been updated to reflect major advances in computer technology, including multicore processors and embedded processors. Interactive simulations have been expanded and keyed into relevant sections of text.

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  • Chapter 1 Introduction
    Chapter 2 Computer Evolution and Performance
    Chapter 3 A Top-Level View of Computer Function and Interconnection
    Chapter 4 Cache Memory
    Chapter 5 Internal Memory Technology
    Chapter 6 External Memory
    Chapter 7 Input/Output
    Chapter 8 Operating System Support
    Chapter 9 Computer Arithmetic
    Chapter 10 Instruction Sets: Characteristics and Functions
    Chapter 11 Instruction Sets: Addressing Modes and Formats
    Chapter 12 Processor Structure and Function
    Chapter 13 Reduced Instruction Set Computers (RISCs)
    Chapter 14 Instruction-Level Parallelism and Super scalar Processors
    Chapter 15 Control Unit Operation
    Chapter 16 Micro programmed Control
    Chapter 17 Parallel Processing1
    Chapter 18 Multi core Computers
    Chapter 19 Number Systems
    Chapter 20 Digital Logic
    Chapter 21 The IA-64 Architecture

    Online Appendices

    Appendix C Hash Tables
    Appendix D Victim Cache Strategies
    Appendix E Interleaved Memory
    Appendix F International Reference Alphabet
    Appendix G Virtual Memory Page Replacement Algorithms
  • Citation

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